This invention relates to a technology for improving an operation speed of a semiconductor memory device. More particularly, this invention relates to a technology that will be effective when used for semiconductor memory devices for which a high-speed operation is required, such as a clock synchronization type SRAM (Static Random Access Memory) and a dynamic RAM.
A memory access time and a cycle time are two important performance factors that determine high-speed performance of semiconductor memory devices such as SRAM (hereinafter called merely the xe2x80x9csemiconductor memoryxe2x80x9d or the xe2x80x9cmemoryxe2x80x9d). The term xe2x80x9cmemory access timexe2x80x9d means the time necessary for an address signal, a clock signal, etc, that are inputted from outside the memory to flow through a path for selecting the memory cell and to output desired data. The term xe2x80x9ccycle timexe2x80x9d means the time of the minimum cycle in which operations such as read and write operations can be executed normally.
FIG. 16 shows the construction of a synchronous SRAM the inventor of the present invention examined prior to the present invention. An address input register 11u holds an address signal inputted from an address input buffer 22u at the timing at which a clock signal changes. A decoder 12u decodes this input address, and corresponding word line WL and bit lines BL, /BL are selected. Consequently, a memory cell MC connected to the selected word line and bit lines causes a read current to flow and generates a small potential difference in the selected bit lines. A sense amplifier 13u amplifies this relatively small potential difference and sends it as read data to an output register 14u. The data is sent from the output register 14u to an output buffer 15u at the timing at which the clock signal reaches the output register, and is outputted outside the memory chip.
Japanese Patent Laid-Open No. 4-28084 discloses a technology that establishes a test mode by elevating Vcc (power source voltage) at the time of a wafer test, decides the activation timing of the sense amplifier in such a fashion as to achieve the highest operation speed on the basis of this test result, and sets permanently this timing by means of programmable elements such as fuses.
To utilize the technology described in this reference, however, the xe2x80x9ctest modexe2x80x9d must be established by elevating the power source voltage Vcc at the time of the test under the wafer state.
In other words, if semiconductor memory devices are assembled after they are confirmed to operate normally under the wafer state, they should certainly operate under such a wafer condition, but their operation is not always guaranteed under conditions other than the wafer condition. Therefore, the test under the wafer condition must be carried out under the condition where read-out of the data of the memory cell to the bit lines gets most retarded in comparison with the sense amplifier activation signal. When the read-out test is carried but under the condition where power source voltage dependence of the speed of the read data signal to the bit lines, that is determined by the memory cell current, and power source voltage dependence of the speed of a latch timing generation circuit of the sense amplifier are different (as is usually the case), for example, the semiconductor memory device is judged as operating normally at a certain power source voltage but is not judged as operating normally at another certain power source voltage. To avoid such a problem, the power source voltage must be freely set and controlled by external signals at the time of the test so that the read condition during the test under the wafer condition becomes the worst within the operation guarantee range.
The result of the examination made by the present inventor has revealed that it is not so easy to satisfy the condition, under which the memory cell read operation becomes the worst as described above, in the prior art example described in Japanese Patent Laid-Open No. 4-28084 because the potential of the power source voltage Vcc must be set to a high level beyond the normal operable range in the xe2x80x9ctest modexe2x80x9d under the wafer condition. After all, the sense amplifier activation timing must be set with a margin of a certain degree, and the highest memory access time the circuit can reach cannot be accomplished easily. Besides the prior art reference described above, mention can be made of Japanese Patent Laid-Open Nos. 7-21776 and 11-3593 that render adjustable the operation timing of the sense amplifier by the use of the set values of fuses and resisters.
These references do not describe the adjustment of the fall timing of the word line or the adjustment of the recovery operation time on the basis of the test result.
To reduce the memory cell access time and the cycle time in the semiconductor memory, it is effective to improve the operation speed of the sense amplifier for amplifying the read signal from the memory cell, for example. A latch type sense amplifier for amplifying a signal of a small amplitude by positive feedback is one of the high-speed sense amplifiers. To exploit fully high-speed performance of this latch type sense amplifier, it is extremely important to generate appropriately a latch activation signal.
FIG. 2 shows an example of the latch type sense amplification circuit the present inventor has examined. If the latch activation signal SALAT is too quick in this circuit, the latch activation signal is generated before the correct data is outputted from the memory cell. In other words, the previous data of the selected memory cell is outputted erroneously. However, if the latch activation signal SALAT is retarded unnecessarily to avoid this erroneous operation, the delay time of the sense amplifier increases.
This problem results after all in the problem how to establish timing between the data read out from the memory cell and the latch activation signal of the sense amplifier. In the conventional semiconductor memories, efforts have been necessary for timing the latch activation signal with the optimal sense latch time determined by the read current of the selected memory cell by constituting the delay circuit by using the same circuit as the circuit, through which the memory cell selection signal passes, and generating the latch activation signal.
However, it is difficult to precisely establishing the timing between the read timing of the memory cell and the timing of the latch activation signal unless characteristics of devices such as MOS transistors are clarified at the time of design. If the actual characteristics of the device are different from the characteristics of the device assumed at the time of design, this difference creates the deviation between the optimal read timing of the memory cell and the latch activation timing. So long as the read path of the memory cell and the delay time path of latch activation cannot be constituted into exactly the same circuit, the times of these paths cannot be made equal to each other. It is therefore necessary to set the latch timing with a margin for the time that is anticipated design-wise, and the problem remains unsolved that the highest memory access time, that the circuit can originally reach, cannot be acquired.
The result of the experiments carried out by the present inventors has revealed that power source voltage dependence of the latch timing of the sense amplifier is greater than that of the data output timing of the memory cell. In other words, the lower the power source voltage, the smaller becomes the margin of the latching timing of the sense amplifier. It is therefore easier to insure the normal operation of the memories over the entire power source voltage range necessary for insuring the normal operation when the test under the wafer state is carried out while the power source voltage is set to a value below the lower limit value of the operation guarantee voltage.
According to the studies of the present inventors, the problems to be solved for improving the speed of the cycle time are as follows.
The first factor that affects the minimum cycle time capable of operating the memory is the time in which the word line rises, that is, the fall timing of the word line. When the memory shifts a certain read operation to a next read operation, the next read operation is sometimes retarded due to the data of the previous read operation unless the bit line opened by the first read operation is completely returned to the initial state. Therefore, the recovery operation must be conducted immediately after, or immediately before, the read operation so that the bit line can be returned to the initial condition. In other words, the two operations, that is, the read operation due to the rise of the word line and the recovery operation of the bit line, must be completed within one cycle. This means that the sum of the time in which the word line is active and the time necessary for the recovery operation governs the minimum cycle time that the memory can reach.
To shorten the cycle time, therefore, it is effective to reduce the time in which the word line rises to the minimum necessary time and to speed up the recovery operation and to shorten it. To this end, it is effective to correctly anticipate the time necessary for keeping the word line active and to set the time in which the word line is active, at the time of design. However, same as the problem concerning the timing of the sense amplifier activation, unless the characteristics of the MOS devices are clarified in detail, it is difficult to anticipate and design correctly this time, and the operation margin must be secured between the actual anticipation value and the design value. The design with such a margin involves the problem that the highest performance that the circuit can ultimately reach cannot be exploited.
It is therefore an object of the present invention to provide a semiconductor memory that can reduce the memory access time and can operate at a higher speed.
It is another object of the present invention to provide a semiconductor memory that can shorten the cycle time and can operate at a higher speed.
It is still another object of the present invention to make it possible to achieve a higher operation speed of both read cycle and write cycle in a semiconductor memory capable of reading and writing data by separately optimizing the cycle time of each of the data read and write operations.
The above and other objects and novel features of the present invention will be come more apparent from the following description of the specification together with the accompanying drawings.
The following will represent the summary of typical inventions among the inventions disclosed in this application.
According to the conventional system that decides the delay route in the design stage, the difference of the delay time occurs unavoidably due to the difference between the anticipated device characteristics in the design stage and the actual device characteristics. Therefore, the present invention includes setting means (such as a fuse circuit) that regulates the timings of various signals inside the chip such as the activation timing of the sense amplifier, the fall timing of the word line, the recovery operation (equalization) timing of the bit line and the sense amplifier, and so forth, in the test stage of the chip after the actual chip is completed, and then programs (fixes) permanently the timings of the internal signals to the condition of the highest operation speed that can be confirmed as achievable in the check stage. Here, the term xe2x80x9crecovery operationxe2x80x9d of the bit lines, the sense amplifier, etc, means that the amplitude of the signal lines, that is expanded by a certain read operation, is quickly reduced by the equalization circuit so as to prepare for a next read operation.
In the present invention, therefore, the whether or not the chip operates normally is confirmed while the timings of the signals are changed after the chip is completed. The timings of the signals inside the chip are fixed to the condition of the highest operation speed that is confirmed as operating, and the chip can be set to the limit normal condition under which the highest performance can be obtained.
The operation guarantee range must be taken into consideration when the memory chip is tested. If the memory chip is confirmed as operating normally under the condition worse than the worst condition among the environmental conditions to guarantee the operation, it becomes possible to confirm that the memory chip operates normally within the full operation guarantee range.
The present invention includes variable check means for regulating the activation timing of the sense amplifier, the fall timing of the word line, the recovery operation (equalization) of the bit line and the sense amplifier, etc, in the test stage of the chip after the actual chip is completed, and checks the operation of the memory chip. Therefore, the present invention can cope with the difference of the anticipated device characteristic values at the time of design from the actual device characteristic values, and can exploit the performance suitable for the device.
The methods for regulating the internal timings in the chip operation test under the wafer state include the method that provides excessive signal input pads, that are not used in the final product, to the chip, and applies a DC voltage to these pads from a tester, the method that stores the regulation information of the timings into a plurality of internal registers from serial input terminals as stipulated by the JTAG (Joint Test Action Group) standard, and so forth. When these methods are employed, the normal operation condition, under which only the timings of the internal signals are changed, can be created without conducting the test by the method that affects the normal operation of the chip, such as the conventional method that changes the power source voltage. Therefore, the test can be conducted by freely changing the operation condition of the power source voltage, and so forth, so that the condition becomes the worst within the operation guarantee range, and the optimum timing of the internal signals can be determined.
In the present invention, the timings of the internal signals of the memory as the regulation object may be as follows.
(1) activation timing of sense amplifier,
(2) non-selection timing of word line,
(3) non-selection timing of Y system selection signals such as column switch,
(4) equalization start timing of bit line, sense amplifier, data bus of post-stage of sense amplifier, etc,
(5) equalization finish timing of bit line, sense amplifier, data bus of post-stage of sense amplifier, etc,
(6) timings (4) and (5) after write and read operations,
(7) set-up and hold time of input circuit in synchronous memory,
(8) clock timing of output latch in synchronous memory. When all, or a part, of these timings is rendered variable, the memory cell access time and the cycle time can be shortened with the result of the high operation speed of the memory.
These timings include the case where their effects can be inspected under the wafer state and the case where the effects cannot be inspected directly under the wafer state. The timings (2) to (4) among them, for example, have the effect of shortening the cycle time, but the internal clock needs not necessarily operate in the high-speed cycle in the inspection stage.
A large parasitic element such as an inductance or an electrostatic capacity couples with the input/output terminals during the inspection under the wafer state. Therefore, it is substantially difficult to operate the chip in the high-speed cycle and to measure correctly the timings among a plurality of input/output signals. An LSI chip containing a memory is generally used after it is assembled into a package. Since the parasitic capacitance of the package and the parasitic capacitance during the inspection under the wafer state are naturally different from each other, it is generally not possible to estimate the measurement result after the assembly into the practical package from the measurement result under the water state.
When the AC characteristics directly associated with the input/output of the chip, i.e. specs such as the set-up time of the data signal with respect to the clock signal and the hold time, or the operation clock of the memory, is inputted from outside the chip, it is not realistic by the existing technologies to elevate the frequency beyond hundreds of MHz.
However, a so-called xe2x80x9cbuilt-in type memoryxe2x80x9d assembled into a microcomputer that multiplies the clock signal inputted from outside by an internal PLL circuit and supplies the signal so multiplied, is free from the limitation described above, and the full speed test can be conducted in some cases from the test stage. In this case, the minimum value of the cycle time can be tested naturally under the wafer state. The present invention does not exclude such a case, and is characterized by including means for controlling the timing of the internal signals in the test stage and means capable of setting the timings to those decided on the basis of the test result.